`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    13:15:53 04/29/2011 
// Design Name: 
// Module Name:    VGAcontrol 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module addresscal(enable1,hcounter, vcounter,blank,addrb);
	//input slw_clk;
	input  enable1;
	wire  [7:0] data;
	input  blank;
	input  [10:0] hcounter, vcounter;
	//output reg [14:0] addra;
	output reg [14:0] addrb;
	//output reg [7:0] vgaout;
	//t_loserpage q4(slw_clk,addrb,data);
		always @(hcounter,vcounter) begin
	
	/*if(enable1 && ~blank)begin
	if(hcounter>=176 && hcounter<463 && vcounter>=165 && vcounter<256) begin
	addra= (hcounter-176)+(vcounter-165)*286;
	end
	else begin
	addra=0;
	end
	end
	else begin
	addra=0;
	end*/
	
	
	if(enable1 && ~blank) begin
	if(hcounter>=248 && hcounter<380 && vcounter>=112 && vcounter<300) begin
	addrb= (hcounter-248)+(vcounter-112)*144;
	end
	else begin
	addrb=0;
	end
	end
	else begin
	addrb=0;
	end
	
	end

	//vgaout= douta;
	

	
	
	
	
	
	
	
	
		
		
endmodule
